A typical off-chip method for measuring an oscillating frequency of a ring oscillator (RO) is to utilize a master/slave flip-flop that has its clock input driven by the RO output. Typically, the RO is included in an integrated circuit (IC) located on a chip, and while the flip-flop is also an on-chip device, it is central and shared among a plurality of ROs, wherein the flip-flop has to reach the plurality of ROs. Flip-flop circuits are typically complex and have a bandwidth that is slow relative to the free-running frequency of a small RO. To measure an operational frequency of a RO with a master/slave flip-flop, the RO is typically scaled up (by adding more stages) so that the frequency at the last stage is lower. However, the overall variation in RO frequency is reduced by adding more stages, which works against the objective of utilizing an RO to facilitate measurement of process variations during manufacture of application-specific integrated circuits (ASICs), for example. In effect, signal variation across the various components of an RO circuit are averaged such that individual variation from a single stage in the RO circuit is masked (e.g., cancelled out) by the variation of the other stages of the RO circuit. Hence, the benefit of incorporating a RO into an ASIC to determine whether the ASIC was manufactured with an expected manufacturing process may be diminished, as the sensitivity of the RO to the variances inherent to the manufacturing process are masked.